CXMT at 10% of DRAM Revenue: What the Figures Show

Counterpoint Research estimates that CXMT's share of global DRAM revenue rose from 4% in Q2 2025 to 10% in Q2 2026. Its intervening estimates are 5%, 8%, and 8%.¹ This measures sales revenue, not bits shipped, wafer capacity, or HBM competitiveness. Counterpoint also reports that total DRAM revenue rose 57% quarter on quarter and 385% year on year in Q2 2026. Price and product mix therefore matter when interpreting the share gain. Another Counterpoint release attributes CXMT's growth to domestic conventional-DRAM demand and expanding capacity; it reports 716% year-on-year revenue growth for CXMT.²

What CXMT has announced

On 20 September 2026, CXMT announced mass production of its G5 DRAM platform. The company reports an 11.95 nm active-area half-pitch, a 45:1 capacitor aspect ratio, and a 6,762 nm core-cell-array height. It says it uses self-aligned quadruple patterning (SAQP) and that gross dies per wafer are at least 50% higher than on its own preceding platform, normalized to an 8 Gb baseline. These are company-reported measurements and comparisons; the announcement provides no independently verified production yield or direct like-for-like comparison with another manufacturer's node.³ A half-pitch alone cannot establish that two complete DRAM processes have equivalent performance, yield, or cost.

CXMT separately announced LPDDR6 mass production on 7 September. Its packaged product has 16 GB capacity, built from 16 Gb dies, and a stated maximum transfer rate of 12,800 Mb/s. CXMT says the product runs at 10,667 Mb/s with the SoC in the Xiaomi 18 Fold. Treating the 12,800 Mb/s product maximum as the demonstrated handset operating rate would overstate the announcement.⁴ Neither the LPDDR6 release nor the G5 release establishes that the LPDDR6 product is made on G5.

Cost, capacity, and HBM: estimates, not measurements

SemiAnalysis estimates that CXMT's DDR5 cost per bit exceeds that of the three leading DRAM suppliers by more than 30%. Its separate HBM3 eight-high model assumes approximately 35% front-end and 70% back-end yield, yielding about 24.5% when multiplied. Both are analyst estimates, not CXMT-disclosed yields or audited cost figures.⁵ A 30% cost-per-bit premium does not imply 30% more wafer starts: cost per bit also depends on die area, die yield, process and equipment cost, depreciation, and product mix. Likewise, 1 / 0.245 ≈ 4.08 is only the expected number of attempted stacks per good stack under that simplified yield model; it is not a measured fourfold total HBM manufacturing-cost premium.

Counterpoint expected capacity to grow from about 320,000 to 420,000 wafer starts per month by 2027 and saw 15% DRAM share as a long-term threshold in its analysis.⁶ Those are forecasts, not achieved output. Revenue share during a price surge cannot be extrapolated linearly into a future bit share.

Public data as of 29 September 2026 do not justify a fixed EUV-driven performance ceiling or a causal claim that SAQP pitch variation sets LPDDR6's observed speed. These are engineering questions, not established explanations for these products.